This workshop is a hands-on, end-to-end practical program designed to bridge the gap between high-level hardware design and physical silicon. Participants will navigate the complete digital ASIC design flow, transforming functional Register-Transfer Level (RTL) HDL code into a tape-out ready GDSII layout using the industry-standard Cadence EDA tool suite.

Beginning with Verilog RTL simulation, attendees will step through logic synthesis, static timing analysis (STA), physical design (floorplanning, placement, clock tree synthesis, and routing), and sign-off verification. Through real-world lab exercises, participants will learn how to resolve timing violations, optimize Power, Performance, and Area (PPA), and validate physical design rules to gain practical experience in modern VLSI chip design.

·         Understand the step-by-step methodologies required to take a digital system from initial specification to tape-out (RTL-to-GDSII).

·       Validate functional correctness and hardware logic using Cadence Xcelium™ / Incisive® simulation environments.Strengthen problem-solving abilities in digital system design by implementing real-world hardware modules and communication interfaces.

·         Translate high-level HDL code into an optimized gate-level netlist using Cadence Genus™ Synthesis Solution, applying appropriate timing constraints (SDC).

·         Master floorplanning, power planning, cell placement, Clock Tree Synthesis (CTS), and signal routing using the Cadence Innovus™ Implementation System.

·         Timing Analysis (STA) with Cadence Tempus™, identifying and fixing setup/hold timing violations across multi-corner scenarios.

·         Gain exposure to industry-relevant RTL design, simulation, verification, and hardware development methodologies.